/*
  Module        : {{ DUT.Module }}
  UMV Component : testbench
  Author        : 
*/

`ifndef {{ DUT.Module | upper }}_TESTBENCH_SV
`define {{ DUT.Module | upper }}_TESTBENCH_SV

// --- UVM --- //
`include "uvm_macros.svh"
import uvm_pkg::*;

// --- Packages --- //
{% if DUT.Dependencies.Packages -%}
    {% for file, package in DUT.Dependencies.Packages.items() -%}
`include "{{ file }}"
import {{ package }}::*;
    {% endfor -%}
{% endif %}
// --- Includes --- //
`include "interface.sv"
`include "sequence_item.sv"
`include "sequence.sv"
`include "sequencer.sv"
`include "driver.sv"
`include "monitor.sv"
`include "agent.sv"
`include "scoreboard.sv"
`include "env.sv"
`include "test.sv"
{% if DUT.Dependencies.Includes -%}
    {% for include in DUT.Dependencies.Includes -%}
`include "{{ include }}"
    {% endfor -%}
{% endif -%}
{# Blank Line #}
`timescale 1ns/1ns
{# Blank Line #}
module top;
  
  // --- Sim Clock --- // 
  logic {{ DUT.Ports.Clock }};
  {{ DUT.Module }}_if {{ DUT.Module }}_intf(.{{ DUT.Ports.Clock }}({{ DUT.Ports.Clock }}));
  parameter CLK_PERIOD = ;

  // --- DUT Instance --- //
  {{ DUT.Module }} DUT(
    // User fills in 
    // Will be added feature in later release
  );
  
  // --- Interface --- //
  initial begin : VIF
    uvm_config_db #(virtual {{ DUT.Module }}_if)::set(null, "*", "vif", {{ DUT.Module }}_intf);
  end
  
  // --- Start Test --- //
  initial begin : TEST
    run_test("{{ DUT.Module }}_test");
  end
  
  // --- Clock Generation --- //
  always begin : CLK_GEN
      {{ DUT.Ports.Clock }} = 1'b1;
      #(0.5 * CLK_PERIOD);
      {{ DUT.Ports.Clock }} = 1'b0;
      #(0.5 * CLK_PERIOD);
  end

  // --- Maximum Sim Duration --- //
  initial begin : TIMEOUT
    #(1000 * CLK_PERIOD);
    $display("Sorry! Ran out of clock cycles");
    $finish();
  end
  
endmodule : top

`endif